An RRAM biasing parameter optimizer

Research on memory devices is a highly active field, and many new technologies are being constantly developed. However, characterizing them and understanding how to bias for optimal performance are becoming an increasingly tight bottleneck. Here, we propose a novel technique for extracting biasing parameters, conducive to desirable switching behavior in a highly automated manner, thereby shortening the process development cycles. The principle of operation is based on: 1) applying variable amplitude, pulse-mode stimulation on a test device in order to induce switching multiple times; 2) collecting the data on how pulsing parameters affect the device’s resistive state; and 3) choosing the most suitable biasing parameters for the application at hand. The utility of the proposed technique is validated on TiOx-based prototypes, where we demonstrate the successful extraction of biasing parameters that allow the operation of our devices both as multistate and binary resistive switches

Emulating short-term synaptic dynamics with memristive devices

Neuromorphic architectures offer great promise for achieving computation capacities beyond conventional Von Neumann machines. The essential elements for achieving this vision are highly scalable synaptic mimics that do not undermine biological fidelity. Here we demonstrate that single solid-state TiO2 memristors can exhibit non-associative plasticity phenomena observed in biological synapses, supported by their metastable memory state transition properties. We show that, contrary to conventional uses of solid-state memory, the existence of rate-limiting volatility is a key feature for capturing short-term synaptic dynamics. We also show how the temporal dynamics of our prototypes can be exploited to implement spatio-temporal computation, demonstrating the memristors full potential for building biophysically realistic neural processing systems

A geographically distributed bio-hybrid neural network with memristive plasticity

Throughout evolution the brain has mastered the art of processing real-world inputs through networks of interlinked spiking neurons. Synapses have emerged as key elements that, owing to their plasticity, are merging neuron-to-neuron signalling with memory storage and computation. Electronics has made important steps in emulating neurons through neuromorphic circuits and synapses with nanoscale memristors, yet novel applications that interlink them in heterogeneous bio-inspired and bio-hybrid architectures are just beginning to materialise. The use of memristive technologies in brain-inspired architectures for computing or for sensing spiking activity of biological neurons8 are only recent examples, however interlinking brain and electronic neurons through plasticity-driven synaptic elements has remained so far in the realm of the imagination. Here, we demonstrate a bio-hybrid neural network (bNN) where memristors work as "synaptors" between rat neural circuits and VLSI neurons. The two fundamental synaptors, from artificial-to-biological (ABsyn) and from biological-to- artificial (BAsyn), are interconnected over the Internet. The bNN extends across Europe, collapsing spatial boundaries existing in natural brain networks and laying the foundations of a new geographically distributed and evolving architecture: the Internet of Neuro-electronics (IoN).Comment: 16 pages, 10 figure

Analog Memristive Synapse in Spiking Networks Implementing Unsupervised Learning

Emerging brain-inspired architectures call for devices that can emulate the functionality of biological synapses in order to implement new efficient computational schemes able to solve ill-posed problems. Various devices and solutions are still under investigation and, in this respect, a challenge is opened to the researchers in the field. Indeed, the optimal candidate is a device able to reproduce the complete functionality of a synapse, i.e. the typical synaptic process underlying learning in biological systems (activity-dependent synaptic plasticity). This implies a device able to change its resistance (synaptic strength, or weight) upon proper electrical stimuli (synaptic activity) and showing several stable resistive states throughout its dynamic range (analog behavior). Moreover, it should be able to perform spike timing dependent plasticity (STDP), an associative homosynaptic plasticity learning rule based on the delay time between the two firing neurons the synapse is connected to. This rule is a fundamental learning protocol in state-of-art networks, because it allows unsupervised learning. Notwithstanding this fact, STDP-based unsupervised learning has been proposed several times mainly for binary synapses rather than multilevel synapses composed of many binary memristors. This paper proposes an HfO2-based analog memristor as a synaptic element which performs STDP within a small spiking neuromorphic network operating unsupervised learning for character recognition. The trained network is able to recognize five characters even in case incomplete or noisy characters are displayed and it is robust to a device-to-device variability of up to +/-30%

Electro-optic Platform for Free Space CMOS Photonics.

Lab-on-chip (LOC) systems are becoming increasingly popular for biomedical science as they present the opportunity to combine compact and efficient microelectronics together with microfluidics enabling new applications in point-of-care diagnostics. This system integration however, poses significant challenges in the assembly of such devices for mass manufacture. Specifically, to achieve a robust fluidic isolation, an insulating material must be deposited to seal the chip and wire bonds but allow fluid to access the sensing surface. This is typically achieved by using an insulating epoxy for encapsulation but requires several processing steps in order to become planar and reliably interface with the microfluidics; a technique with many limitations. Towards addressing these challenges, this thesis proposes to develop a non-galvanic means of achieving both power transfer to the chip and bi-directional data communication such that the system requires no bond pads (or delicate bond wires). The aim is to achieve this specifically via a free space optical link (i.e. to external discrete optoelectronic devices) with the additional constraint that any structures designed on chip are implementable in a commercially available, unmodified CMOS technology. Furthermore, in order to maintain the desired benefits of a “bondpad-less” chip, the platform must utilise no off-chip components. This thesis develops the underlying devices required towards achieving the aim whilst satisfying all constraints. Specifically devices tasked with optical energy harvesting, optical data input and optical data output are tackled. The thesis begins by outlining the motivations for this research (Chapter 1) and reviewing the relevant state-of-the-art (Chapter 2) including a concise overview of alternative methods for achieving the underlying aims. The relevant theory, pertinent to electro-optical phenomena at semiconductor junctions is then developed within the context of CMOS technology (Chapter 3). More fundamental, background theory is also included in appendix A. That pertains to the propagation of light in Silicon and mechanisms of photon absorption in doped Silicon. Original contributions within the domain of theory include developing the phenomenon of free-carrier absorption (FCA) applied to a realistic, CMOS-based junction, identifying key variables, expressions and analyzing the expected level of performance. Then, for the first time, this thesis demonstrates free-space optical modulation in a standard CMOS technology. A large portion of this work (Chapter 4 - for design repository see appendix B) is thus devoted to the design, implementation and testing of prototype devices for use as data read-out elements. A variety of modulator devices featuring differing geometries, created by distinct doping procedures and implemented in different CMOS technological nodes (UMC 0.13 [mu]m, IBM 0.18 [mu]m and AMS 0.35 [mu]m) are presented, tested and compared. This allows for modulator performance to be examined in relation to key design choices made at the physical device layout and technology choice levels. This thesis then develops the common data read-in and power scavenging mechanism, along with associated circuits (Chapter 5). Once again structures designed with different geometries and created by different manufacturing processes in different technological nodes are presented, tested and compared, yielding an indication towards underlying trends. Key contributions here include extracted photodiode model parameters that express the contributions of vertical and lateral junction components to photocurrent generation, by junction 'family' and by CMOS process. This provides a powerful resource to circuit designers requiring a first estimate to phototransduction efficiency in technologies with unspecified optoelectronic devices.Open Acces

Dataset for: A computationally efficient Verilog-A ReRAM model

Data set for paper of same name. This is a Verilog-A ReRAM model that corresponds to the behavior of a physical TiO2-based sample manufactured in Nano Group, ECS, University of Southampton. The model is ready for use and can be compiled in any electronics circuit simulator that supports Verilog-A models.</span